Page Tables
The map from virtual page to frame (or disk). Multi-level to keep them sparse.
Level: intermediate
What is it?
A page table maps virtual pages to physical frames and stores status and protection information such as present, writable, user-accessible, and execute permissions. The MMU consults these entries during address translation, often through a cached translation lookaside buffer.
Why does it matter?
Page tables create per-process virtual address spaces and enforce isolation. Their storage and lookup cost would be large for sparse address spaces if every possible virtual page required a flat entry, so multi-level or other hierarchical structures are common.
Mental model
Split a virtual address into a virtual page number and page offset. The page table translates the page number; the offset selects a byte within the resulting frame.
How it works
- The page offset stays the same when a virtual page maps to a physical frame of the same page size.
- Page-table entries can describe absent pages as well as present physical mappings.
- Multi-level page tables allocate lower-level tables only for used address ranges, reducing overhead for sparse mappings.
- Permissions are checked during translation and can raise a fault even when a physical frame exists.
- Changing mappings may require TLB invalidation on one or more CPU cores to avoid stale translations.
Steps
- A process references virtual address V.
- The MMU separates V into page number and offset.
- The TLB is checked; on a miss, hardware or the kernel walks the page-table hierarchy.
- The mapping and permissions are checked, and the frame address is combined with the offset.
Real-world usage
- Explaining virtual-to-physical address translation.
- Reasoning about multi-level page-table memory overhead.
- Diagnosing protection faults and TLB invalidation issues.
Common mistakes
- Changing a page mapping without accounting for cached translations.
- Assuming a page-table entry contains the entire virtual address.
- Confusing a page fault (missing or invalid mapping) with a TLB miss (translation not cached).
Interview questions
What is stored in a page-table entry?
Typically a physical frame number plus mapping status, access permissions, and architecture-specific flags.
What is the difference between a TLB miss and a page fault?
A TLB miss means the translation is not cached and may be found in the page table. A page fault means the access cannot complete under the current mapping and requires OS handling.