TLB
A cache of page-table entries so every load does not walk the page table.
Level: intermediate
What is it?
A translation lookaside buffer (TLB) is a small, fast cache of recent virtual-to-physical address translations. The CPU checks the TLB during memory access; on a miss, it performs a page-table walk or invokes architecture-specific handling before caching the translation.
Why does it matter?
Without a TLB, memory references may require several extra memory accesses to walk multi-level page tables. TLB hit rate therefore strongly influences effective memory latency for workloads with a large or irregular working set.
Mental model
Think of the TLB as a cache of address translation answers. It does not cache the data being read; it caches the map telling the CPU where the data page lives and whether that access is permitted.
How it works
- TLB entries may be tagged with address-space identifiers so mappings from multiple processes can coexist safely.
- Context switches may require TLB invalidations on systems without suitable address-space tags.
- Changing page permissions or mappings requires invalidating stale entries, sometimes across multiple CPU cores.
- Huge pages can increase TLB reach by mapping more memory per entry, but have allocation and fragmentation trade-offs.
- A high TLB miss rate can arise from poor locality, a large active page footprint, or excessive context switching.
Steps
- The CPU issues a virtual address and checks the TLB.
- On a hit, the cached frame and permission information support translation immediately.
- On a miss, the page table is walked and the mapping is validated.
- The valid translation is inserted into the TLB; the original memory access then continues.
Real-world usage
- Explaining effective memory-access time.
- Profiling pointer-heavy or memory-intensive workloads.
- Understanding TLB shootdowns and address-space isolation.
Common mistakes
- Calling a TLB miss a page fault every time.
- Ignoring permission bits cached with the translation.
- Updating mappings without invalidating stale TLB entries.
Interview questions
What does a TLB cache?
Recent virtual-page translations and associated attributes, rather than application data bytes.
Why can a page-table update require a TLB shootdown?
Other CPU cores may hold cached translations for that address space; invalidating them prevents stale mappings or permissions from being used.